The present invention generally relates to integrated circuits and, more particularly, is related to simplifying clock construction and clock distribution within an integrated circuit, in addition to simplifying analysis of the clock in the integrated circuit.
Many integrated circuits (IC) are synchronous circuits wherein the IC is synchronized by clock signals. Clock signals are typically provided by a clock generator located within the IC that provides clock signals to logical blocks located within the IC. The logical blocks located within the IC differ in accordance with functionality made available by the IC.
Prior to fabrication of an IC, the IC is typically created in software to enable testing of IC electrical characteristics and functionality. To enable testing of the IC, logical blocks within the IC are arranged by a circuit designer in accordance with either, a known predefined schematic, or simply in a random arrangement that allows all logical blocks to fit upon the IC. An example of a program that may be utilized to simulate placement of the logical blocks on the IC is the IC layout tool MAGIC, developed by Berkeley. Of course, other IC layout tools may be utilized as well.
After placement of logical blocks upon the IC, the clock generator is added to the IC and interconnect is mapped within the IC, from the clock generator to the logical blocks, thereby distributing a clock signal to each logical block. Clock signal buffers may be utilized within the IC to assist in driving clock signals to the logical blocks.
After completion of the IC layout, electrical characteristics and functionality of the IC may be tested. An example of an IC simulation program that may be used to test the electrical characteristics and functionality of the IC is simulation program for integrated circuit emphasis (SPICE). Of course, other IC simulation programs may be utilized as well.
It is desirable for the clock signal to arrive at the logical blocks simultaneously to effectively provide a synchronized IC. If, however, the clock signal is received by different logical blocks, at different times, the difference in clock signal arrival time may be accounted for during designing of the IC. While multiple methods may be utilized to compensate for the difference in clock signal arrival time, one method utilized is to account for the difference, or skew, as additional setup or hold time to be added to the IC during design of the IC. An example of a method that may be utilized to add additional setup or hold time to the IC is modifying characteristics of a clock buffer that is utilized to drive the clock signal from the clock generator to the logical blocks.
Since the fabrication method described above requires waiting for placement of logical blocks before clock generator placement and clock signal distribution, testing of the IC can not be effectively performed until after logical blocks have been placed, the clock generator has been placed, and the clock has been distributed from the clock generator to the logical blocks. Unfortunately, requiring a delay to testing of the IC until after placement of logical blocks, the clock generator, and distribution of the clock results in a delay to manufacturing and distribution of the finalized IC.
In addition, since clock distribution is dependent upon placement of the logical blocks, as has been explained above, it is difficult to utilize the same clock distribution pattern for more than one IC. Since the same clock distribution pattern may not be utilized for more than one IC, each new IC demands an allotment of time to design and fabricate a new clock distribution pattern.
In light of the foregoing, the preferred embodiment of the present invention generally relates to a system for simplifying clock construction and distribution within an IC, and simplifying analysis within the IC.
Generally, with reference to the structure of the clock distribution system, the system utilizes a memory; software stored within the memory defining functions to be performed by the system; and a processor. The processor is configured by the software to perform the steps of: reading a defined location for a clock generator within the integrated circuit, wherein the clock generator generates a clock signal; reading a defined number of interconnect routes to be created within the integrated circuit, wherein a subset of the number of interconnect routes corresponds to a number of logical blocks that will later be provided within the integrated circuit, and wherein each of the interconnect routes within the subset comprises an open end for one of the logical blocks to be placed; testing electrical characteristics and functionality of the integrated circuit to ensure that a time for the clock signal to traverse each of the interconnect routes is equal, and changing properties within the integrated circuit if the clock signal traversal time is not equal; and adding the logical blocks to each of the interconnect routes within the subset, wherein each of the logical blocks is connected to the open end of one of the interconnect routes within the subset.
The present invention can also be viewed as providing a method for simplifying clock construction and analysis of a integrated circuit. In this regard, the method can be broadly summarized by the following steps: defining a location for a clock generator within the integrated circuit, wherein the clock generator generates a clock signal; defining a number of interconnect routes to be created within the integrated circuit, wherein a subset of the number of interconnect routes corresponds to a number of logical blocks that will later be provided within the integrated circuit, and wherein each of the interconnect routes within the subset comprises an open end for one of the logical blocks to be placed; testing electrical characteristics and functionality of the integrated circuit to ensure that a time for the clock signal to traverse each of the interconnect routes is equal, and changing properties within the integrated circuit if the clock signal traversal time is not equal; and adding logical blocks to each of the interconnect routes within the subset, wherein each of the logical blocks is connected to the open end of one of the interconnect routes within the subset.
Other systems and methods of the present invention will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present invention, and be protected by the accompanying claims.